Designing Network On-Chip Architectures in the Nanoscale Era (Chapman & Hall/CRC Computational Science)
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US$20.70
Price when purchased online
Free shipping
Free 30-day returns
Sold and shipped by mezacontable.com
Free 30-day returns Details
Product details
| Management number | 231603219 | Release Date | 2026/06/18 | List Price | US$20.70 | Model Number | 231603219 | ||
|---|---|---|---|---|---|---|---|---|---|
| Category | |||||||||
Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.Exploring the design process of the Read more
| ASIN | B00OD4K7QG |
|---|---|
| XRay | Not Enabled |
| Format | Print Replica |
| ISBN13 | 978-1439837115 |
| Edition | 1st |
| Language | English |
| File size | 14.3 MB |
| Page Flip | Not Enabled |
| Publisher | Chapman and Hall/CRC |
| Word Wise | Not Enabled |
| Print length | 528 pages |
| Accessibility | Learn more |
| Part of series | Chapman & Hall/CRC Computational Science |
| Publication date | December 18, 2010 |
| Enhanced typesetting | Not Enabled |
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